The present invention relates generally to data communication switching systems and more particularly relates to a cross bar switching matrix having improved broadcast performance via the utilization of broadcast buffering and management.
More and more reliance is being placed on data communication networks to carry increasing amounts of data. In a data communications network, data is transmitted from end to end in groups of bits which are called packets, frames, cells, messages, etc. depending on the type of data communication network. For example, Ethernet networks transport frames, X.25 and TCP/IP networks transport packets and ATM networks transport cells. Regardless of what the data unit is called, each data unit is defined as part of the complete message that the higher level software application desires to send from a source to a destination. Alternatively, the application may wish to send the data unit to multiple destinations.
Currently, many switching systems utilize switching fabrics or matrixes that are designed to switch variable length packets of data. The variable length of packets in these switching systems, however, offer larger and less predictable switching delays as packet switching is more complex than fixed length packet switching.
The transmission of data to a single destination is termed unicast data while the transmission of data to all destinations is termed broadcast data. The transmission of data to a select number of destinations larger than one is termed multicast data. In an example switching system, each call connection within the switch has associated with it a routing tag or equivalent that functions to identify the destination for the packet.
For unicast connections, the routing information identifies a single destination for the packet. For broadcast connections, the routing information identifies the packet as a broadcast packet that is to be distributed to all output ports. For multicast connections, the routing information identifies several destinations for the packet.
A majority of data communication networks today attempt to not lose even a single bit of information in transmitting data from one point to another. In order to achieve such high levels of performance and low error rates, the network equipment is constructed with relatively large sized queues. The large queues are needed in order to handle the accumulation of packets without overflowing the queues. An overflow of a queue will result in packets being lost, i.e., dropped. Packets may be dropped at the source queue if the destination is full and thus cannot receive additional packets. In this case, the source queue fills up and at some point will overflow, with consequent packet loss.
A problem arises, however, with the transmission of broadcast packets through the switching matrix. In prior art switching systems, the switch must wait until the matrix tracks are cleared before a broadcast packet can be transmitted through the switch. All the output ports of the switch matrix must be free before the broadcast packet can be transmitted. This results in very large delays, which greatly reduces the efficiency and throughput of the switch matrix. The following example illustrates this problem.
A block diagram illustrating an example prior art crossbar switch matrix capable of handling unicast, broadcast and multicast traffic is shown in FIG. 1. The switching system, generally reference 10, comprises a plurality of input/output (I/O) interface (I/F) cards 12 having a plurality of PHY interfaces, labeled 1 through N, and a plurality of outputs, labeled 1 through N. The system 10 further comprises an Nxc3x97N crossbar switch matrix 14 having N input ports and N output ports. The N outputs of the I/F cards 12 are coupled to the N input ports of the switch matrix 14. The N output ports of the switch matrix 14 are input back to the I/F cards 12. A controller 16 functions to control the configuration of the switch matrix 14 at any particular point in time via one or more control lines 18 labeled CNTRL.
The crossbar switch is required to switch the entire set of input ports to the output ports in accordance with configuration information from the controller 16. The controller 16 is responsible for providing the appropriate configuration information to the crossbar switch matrix 14 at the correct time. The crossbar switch 14 performs the switching operation in accordance with the switching information provided by the controller. In the event a broadcast packet is to be transmitted from any of the I/F cards, the configuration controller 16 provides the appropriate switching commands which cause the broadcast packet to be transmitted to all the output ports. This is achieved by the issuance of the suitable configuration commands to each I/F card. All I/F cards (except the one transmitting the broadcast packet) and all the input ports will be in the idle state for a broadcast transmission to occur.
In operation, the format of the received signal is converted to packets and forwarded to the ingress of the switching matrix. The I/F card determines a destination output port on the switch matrix for input data received over the PHY I/O channel.
When packets are output of the switch matrix, they return to the I/F card corresponding to the output port. The packet is then output to the PHY via a PHY interface.
A disadvantage of this prior art switching architecture is that the transmission of broadcast packets occurs only when all the input ports are in the idle state, i.e., they are not in the middle of transmitting a packet of data. In addition, during the transmission of a broadcast packet, all the I/F cards, except the one transmitting the broadcast packet, are also in the idle state. Since the switch is constructed to transmit variable length packets, the waiting time until all the I/F cards and input ports are in the idle state, i.e., have completed their current packet transmissions, is also variable and may be very long. An illustration of this problem is provided below.
A diagram illustrating the timing of the transmission of packets through a prior art switch matrix before and after a broadcast packet is scheduled for transmission is shown in FIG. 2. Assume that prior to the point in time represented by reference arrow 20 in FIG. 2, that each input port is in the midst of receiving a data stream comprising variable length packets. Each line represents a different egress output port from the switch matrix. The output ports comprise output ports #1 through output ports #N but only output ports #1 through #5 and #N are shown for clarity sake. The switch matrix creates a traffic stream from input ports to output ports.
Assume also that at time represented by reference arrow 20, a controller on the switch matrix is notified of a broadcast packet ready for transmission in one of the I/F cards. At this point, the controller ceases starting any new packet transmissions and waits until the busy ports finish their transmissions of the current packet. After the last port has completed transmission, the controller configures the switch matrix to transmit the broadcast packet to all the output ports. Once the broadcast packet has completed transmission through the switch, new packets queued up in each of the I/F cards begin transmission through the switch matrix to the output ports and normal unicast packet flow resumes.
With reference to FIG. 2, the waiting time TW can be relatively large compared to the transmission time of some of the packets. The controller must wait for the longest length packet to finish transmission before sending the broadcast packet. The waiting time TW in this case extends from the end of the packet output from port #5 to the end of the packet output from port #4. Only at that point can the broadcast packet 22 be transmitted through the switch. The time of transmission of the broadcast packet is denoted by TBC. The waiting time TW, i.e., unutilized slot time, before transmitting the broadcast packet causes a large decrease in performance. This problem is even more acute when the switch is capable of operating at very high speeds.
The present invention is a crossbar switching system that utilizes broadcast buffering and broadcast buffer management to improve the transmission of variable length broadcast packets through a switch. The invention provides for greatly increased performance when transmitting broadcast packets through a switch matrix. The invention achieves this by halting the transmission of unicast traffic and transmitting a plurality of broadcast packets consecutively. Once the broadcast packets have finished transmission, unicast packet transmission resumes.
The invention achieves improved performance by consecutively transmitting many broadcast packets at a time, thus reducing the lengthy time waiting overhead typically associated with stopping unicast transmission and transmitting a single broadcast packet.
A broadcast buffer or queue is placed on each interface card for storing broadcast packets during unicast transmission. In a first embodiment, a broadcast buffer management unit is also provided on each I/F card and controls the operation of the broadcast buffer.
In a second embodiment, the switching system only comprises a single broadcast buffer management unit, located on the switch matrix, for example, and is adapted to provide control of the broadcast buffers on each interface card.
Note that the crossbar switch matrix of the present invention is applicable to any switching matrix that is adapted to switch variable length data units, e.g., packets, frames, etc. The invention is applicable to both electrical and optical switches, wherein in the latter case, the optical based physical transmission signals are converted from optical to electrical before arriving at the crossbar matrix and are converted back to optical after egressing from the crossbar matrix.
There is provided in accordance with the present invention a crossbar switching system for use with variable length unicast and broadcast packets comprising an Nxc3x97N crossbar switch matrix comprising N input ports and N output ports, the switch matrix adapted to couple data present at any input to any output port in accordance with switch configuration commands and N interface (I/F) circuits, each I/F circuit coupled to a corresponding input port on the switch matrix, each IF circuit comprising N unicast queues, each unicast queue coupled to a corresponding output port on the switch matrix, a broadcast buffer coupled to the corresponding output port on the switch matrix and adapted to store a plurality of broadcast packets and a broadcast buffer management unit adapted to periodically halt the transmission of unicast packets to the crossbar switch matrix to permit the consecutive transfer of broadcast packets thereto, the broadcast buffer management unit adapted to store broadcast packets arriving to the I/F circuit in the broadcast buffer, the broadcast buffer management unit operative to consecutively transfer the contents of the broadcast buffer to the crossbar switch matrix while the transmission of the unicast packets is suspended, the transmission of the unicast packets resuming following the completion of transmission of the broadcast packets.
There is also provided in accordance with the present invention a crossbar switching system for use with variable length unicast and broadcast packets comprising an Nxc3x97N crossbar switch matrix comprising N input ports and N output ports, the switch matrix adapted to couple data present at any input to any output port in accordance with switch configuration commands, the crossbar switch matrix comprising a management bus adapted to send and receive a plurality of broadcast buffer management control and status signals, a broadcast buffer management unit coupled to the management bus, N interface (I/F) circuits, each I/F circuit coupled to a corresponding input port on the switch matrix, each I/F circuit comprising N unicast queues, each unicast queue coupled to a corresponding output port on the switch matrix, a broadcast buffer coupled to the corresponding output port on the switch matrix and coupled to the management bus, the broadcast buffer adapted to store a plurality of broadcast packets and wherein the broadcast buffer management unit adapted to periodically halt the transmission of unicast packets to the crossbar switch matrix to permit the consecutive transfer of broadcast packets thereto, the broadcast buffer management unit adapted to store broadcast packets arriving to the I/F circuit in the broadcast buffer, the broadcast buffer management unit operative to consecutively transfer the contents of the broadcast buffer to the crossbar switch matrix while the transmission of the unicast packets is suspended, the transmission of the unicast packets resuming following the completion of transmission of the broadcast packets.